Performance evaluations of 3/sup rd/ order sigma-delta (/spl Sigma/ - /spl Delta/) modulators via ASIC implementation

A third-order sigma-delta (/spl Sigma/ - /spl Delta/) modulator implementation in a Digital Power Amplifier is presented in this paper. The operation is obtained by using a novel combination of architectural features, proper circuit structure selections, specific clocking strategies, and efficient circuit optimization algorithms. Measurement results from fabricated CMOS chip prototypes show a good match with simulations.