Functional verification methodology of a 32-bit RISC microprocessor

With the increasing complexity of Microprocessor, the verification of the design becomes more and more important. This paper presented a simulation-based functional verification methodology to validate a 32-bit RISC microprocessor (named as FDU32). In the paper, pseudo-random generating and pipeline-focus generating are used as the main method to generate testbenches. Besides, the whole verification environment is set up to improve the automation and efficiency of the process. In addition, code coverage analysis is used to guarantee the quality of the verification.