HDL driven chip layout within the FHDL design framework

Techniques of automatically generating layout from Florida Hardware Design Language (FHDL) specifications are presented. These techniques allow for the automated layout of read-only memories (ROMs) and programmable logic arrays (PLAs), and they allow for the user-assisted automatic layout of standard-cell blocks. Adaptations of the FHDL and its framework to permit layout synthesis are presented. Cell generation is discussed. Adapting the simulation framework and primitive simulation modelling are discussed.<>