CMOS standard cells characterization for I/sub DDQ/ testing

This paper describes the CMOS standard cells characterization methodology for I/sub DDQ/ testing. Defect statistics were taken into account and critical area approach was used to generate compact test sets. The proposed methodology allows one to find the types of faults which may occur in a real IC, to determine their probabilities, and to find the input test vectors which detect these faults. Experimental results for gates from an industrial standard cell library were presented. The complete bridging fault set and different types of the simulation conditions of shorts at inputs of logic gates ("Wired-AND" and "Wired-OR" conditions) were considered.