A reconfigurable systolic primitive processor for signal processing

Recent developments in the area of logarithmic number systems have demonstrated that when properly configured, floating point precision can be achieved at fixed point speeds. To overcome the 12-bit historical address space limit of high speed lookup memory devices, a new Adaptive Radix Processor is proposed and an error analysis is performed. Interconnecting a number of identical ARPs, fast and compact DSP systems can be designed operating on a low error budget over a large dynamic range. Examples are presented using a "shared memory design. Finally, due to identical processors used in the designs reconfiguration can be used to fully utilize the available hardware and/or introduce a degree of fault tolerance.