A low-power UHF RF frontend for a low-IF receiver

A low-power 435 MHz RF front end was implemented in a 0.5 /spl mu/m CMOS process that is intended for use in a low-power low-IF receiver under development for deep space communication. The RF front end includes a differential low-noise amplifier (LNA) with on-chip spiral inductors and a doubly balanced mixer which downconverts the LNA output to 2 MHz IF. The front end has a simulated noise figure of 3.8 dB, input 1-dB compression point of -42 dBm, input third-order intercept point of -34 dBm, and conversion gain of 54 dB. Total power dissipation is 15 mW. The area occupied by the chip is 1.3 mm /spl times/ 1.9 mm.