Parallel interface ICs for 120Mb/s fiber optic links

INTEGRATION OF ANALOG AND DIGITAL functions on the same chip has obvious advantages in reduction of system complexity and cost. The risk inherent in this operation is the degradation of analog performance by logic system crosstalk. High frequency phase-locked loops (PLLs) are a particularly susceptible analog component. Their voltagc-controlled oscillators can be injection locked or pulled by sources of interference, increasing their phase noise to unacceptable levels. This paper will describe silicon bipolar transmit and receive interface ICs for 12OMb/s serial data links that integrate PLLs for clock generation and recovery with logic that performs parallel-to-serial conversion, line coding and decoding, frame synchronization, and link monitor functions.