An ECL 2.8ns 16K RAM with 1.2K logic gate array

AN ECL 16Kb bipolar SRAM with 1248 logic gates in an array using a U-groove IOP-II (Isolation by Oxide and Polysillicon) isolation, a 1.0μm design rule and three layers of metallization, will described. The RAM has a typical access time of 2.8ns, and has a typical write pulse width of 2.5ns with power dissipation of 4.4W. The gate has a basic propagation delay time of 280ps with a power dissipation of 2.2mW/ gate. The die is housed in a 180-pin flat package.