A 20ns static column 1Mb DRAM in CMOS technology

RECENT DEMANDS FOR DRAMs involve not only LSI, but high-speed column functions with reduced power consumption. This performance can best be accomplished by CMOS because of its low power dissipation and high-speed characteristics. This paper will report the development of a 1Mb static column DRAM using a back bias generator in N-well CMOS technology, with a column address access time of 20ns, a RAS access time of less than 80ns, and power dissipation of 230mW at 210ns cycle time.