A 1Mb ROM with on chip ECC for yield enhancement

A 1Mb PROGRAMMABLE ROM, with on-chip ECC(Error-Correcting Code) circuits for yield enhancement and an on-chip substrate bias generator for high speed, fabricated by polycide gate 2μ N-well CMOS technology, will be described. Organized as 128Kx8b, the ROM occupies an area of 78.8mm^2. and is assembled in a 600-mil wide 28 pin DIP, as shown in Figure 1