A subnanosecond cycle time chip in Josephson technology

THIS PAPER will describe the design and performance of a subnanosecond cycle time logic chip in Josephson technology. A data processing circuit, implemented in 2.5pm Josephson Current Injection Logic (CIL)1 has been tested at cycle times as small as 665ps The chip power dissipation was about 350pW. The circuit contained OR gates, AND gates, EX-OR gates and latches - equivalent to 102 logic gates, consisting of 177 devices. The gates were powered by an ac power supply2 which was regulated on chip3. The latch circuits were of a self-resetting type, designed for this application.