MISER: an integrated three layer gridless channel router and compacter

Presented is a new gridless, three-layer channel router (MISER) based on an integrated approach to routing and compaction in VLSI design. MISER partitions the input net-list into several sub-net-lists called levels and forms a level-graph. This level-graph is used to guide the routing and compaction process. Compaction is done immediately after each level is routed. Experimental results show that the algorithm usually performs 5-10 % better than existing three-layer channel routing algorithms.<
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