Timing verification using HDTV

A system designed for verifying the consistency of timing specifications for digital circuits is presented. The utility of the system comes from the need to verify that existing digital components will interact correctly when placed together in a system. To perform this interface verification, two operators are defined which allow one to perform useful reasoning concerning the interface. One operator deals with causality and another with timing constraints. The system can also be used in the case of verifying specifications of unimplemented components. The system is implemented as a hardware design timing verification (HDTV) program.<
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