MHERTZ: a new optimization algorithm for floorplanning and global routing

Timing-driven placement is essential for full-custom VLSI, gallium arsenide, and ECL circuits to meet wire timing constraints. A new macro/custom cell floorplanner and global router, called MHERTZ, is described. It meets wire timing constraints by using force-directed cost functions in multistart and simulated annealing (SA) optimization algorithms. MHERTZ also prevents wire coupling, meets specified chip aspect ratios, and produces smaller floorplans than TIMBERWOLFMC.<
>