VLSI Node Processor Architecture for Ethernet

The VLSI Ethernet controller chips are discussed from a designer's viewpoint. Their method of operation is explained and design tradeoffs are presented with concentration placed on memory response requirements, memory location options relative to the VLSI devices, and the effects of FIFO depth on performance. A "common sense" architecture for an Ethernet node processor with application to many classes of Ethernet nodes is suggested to conclude the paper.