Fatigue Life of Leadless Chip Carrier Solder Joints During Power Cycling

An ana1ytica1 method is described which provides estimates to first order of the number of either power or envirnnmenta1 cyc1es 1eading to so1der joint fai1ure. Vari0us parameter variations such as so1der joint height, ceramic chip carrier (CCC) size, printed c1rcuit substrate (PCS) materia1, etc. are investigated and discussed and samp1e estimates for a 0.65 x 0.65-in CCC are given.