Pseudo epi-cost reduction approach and a paradigm shift in substrate material

Historically, P/P+ epitaxial wafers have been utilized for CMOS products for more than two decades. The epitaxial wafers have several key characteristics such as latch up immunity, oxygen-free active areas, superior oxide quality, and gettering capability compared to bulk nonepi wafers. The epi wafers, however, are costly. Pseudo epi is an alternative to epi wafers with equivalent device performance and material cost savings of 20%-25%. Pseudo epi or high-temperature hydrogen anneal is expected to save a significant percentage of start material costs over the epi substrate for logic family products where epi wafers have dominated the market.