Memory design for bit-level VLSI architectures

Many algorithms make use of memories for table lookup of functions. Parallel implementations of these algorithms require the parallelizing of the table-lookup function. Some of the issues involved with mapping such algorithms to highly parallel VLSI arrays are examined. Reading memory may be viewed as a census function, which is usually and most optimally implemented with tree structures. A parameterized memory algorithm which may be compiled such that it maps to a VLSI architecture which satisfies some notion of optimality is proposed. Optimally pipelining a memory read function is demonstrated, and issues of designing decoders to minimize VLSI cost measures are discussed. The design method is particularly well suited for bit-pipelined, multiport, and content-addressable memories.<>