A 1-GS/s 12-bit Pipelined-SAR ADC With Dither-Based Background Calibration of Interstage Gain and Comparator Offset in 28-nm CMOS

This paper presents a 12-bit, two-stage, 1GS/s pipelined-SAR ADC in 28-nm CMOS. The design leverages an open-loop amplifier and an alternate-comparator SAR ADC to enhance speed and power efficiency. A dither-based background calibration scheme is proposed to mitigate gain and offset errors with minimal hardware overhead and no timing penalty. The gain error calibration reuses the sub-ADC to resolve additional bits for interference cancellation, enabling fast convergence. The offset calibration directly tunes the relative offset between alternate comparators based on LSB distribution. The prototype achieves a signal-to-noise-and-distortion ratio (SNDR) of 60.1 dB and a spurious-free dynamic range (SFDR) of 75.7 dB with a Nyquist input. With interference cancellation, the gain calibration convergence is accelerated from $4.4\times 10 {^{{6}}}$ to $1.0\times 10 {^{{6}}}$ cycles. It consumes 14.72 mW from a 1V supply. The corresponding Schreier and Walden figure-of-merit (FoM) values are 165.4 dB and 17.8 fJ/conv.-step, respectively.