A Standardized 20-Tb/s Bandwidth Scalable Heterogeneous 2.5-D System Supporting Assembly Time Workload-Dependent Chiplet Configurations

The increasing adoption of chiplet-based architectures highlights the compelling paradigm of disaggregating monolithic systems into interconnected chiplets, offering numerous advantages for heterogeneous integration. This disaggregation is essential as chips approach the reticle limit, improving yield and design flexibility by combining diverse functionalities. Next-generation 2.5-D systems require enhanced interoperability across heterogeneous multi-foundry nodes, higher memory, I/O, and scalable interconnects for varied chiplet types driven by artificial intelligence (AI) and data-intensive workloads. We introduce a unique 2.5-D packaging approach integrating heterogeneous multi-foundry active chiplets over a large passive base in silicon (PBS) chiplet. Our system in package (SIP) houses up to 20 ( ${\sim } 4\,{\times }\,4$ mm) chiplets, demonstrating significant and functional heterogeneous integration and scalability beyond reticle limits, addressing integration complexities. This platform enables the creation of highly customized compute systems tailored to specific application demands. Furthermore, the high bandwidth and energy efficiency facilitate complex data processing and acceleration. To tackle memory bottlenecks in AI, future systems should enable workload-tailored assembly for optimal heterogeneous resource allocation. Our SIP achieves 20-Tb/s aggregate bandwidth in parallel computing across heterogeneous units with 0.8-pJ/bit die-to-die (D2D) efficiency, showcasing potential for high-performance, power-conscious heterogeneous disaggregated systems.