Impact of Aging, Self-Heating and Parasitics Effects on NSFET and CFET

This work presents a comparative analysis of Complementary Field-Effect Transistor (CFET) and Nanosheet FET (NSFET) architectures, with a focus on self-heating effects (SHE), Negative Bias Temperature Instability (NBTI), Hot Carrier Degradation (HCD), and the impact of Back-End-of-Line (BEOL) parasitics on standard cell performance. NBTI degradation is modeled using a framework combining Reaction-Diffusion (RD) and Reaction-Drift-Diffusion (RDD) mechanisms in TCAD. BEOL parasitics are extracted using TCAD-generated structures. Both the CFET and NSFET exhibit similar degradation behavior under NBTI stress. However, CFETs show more pronounced degradation due to HCD, primarily driven by stronger SHE. Next, we simulate CFET and NSFET-based 3D inverters and SRAM structures in TCAD, with BEOL interconnects up to M3 level, to study the impact of parasitics on the circuit performance. Meanwhile, CFETs offer ~50% area savings at the standard cell level and lower parasitics, leading to a 42% improvement in inverter propagation delay. The SRAM cells based on CFETs are also evaluated and compared against NSFET in terms of area, noise margins, and performance. CFET SRAM cell provides area gain along with faster and more stable write operation, providing a potential advantage in high-performance applications as compared to NSFET.