A 42-Gb/s Noise-Tolerant Single-Ended Clock-Referenced PAM3 Transceiver for Chiplet Interfaces

This article describes a single-ended (SE) clock-referenced PAM3 (CR-PAM3) transceiver that achieves an energy efficiency of 0.275 pJ/b at a high data rate of 42 Gb/s. The proposed CR-PAM3 signaling provides tolerance to supply noise and reference offset in SE chiplet or die-to-die (D2D) interfaces by using forwarded clock as reference voltages instead of generating them at the RX side. To minimize power consumption for PAM3, a differentially weighted data driver is employed. The proposed XTC-combined FS-puller helps voltage level transition while canceling FEXT from adjacent channels. A decision feedback equalizer (DFE)-embedded sampler enables low-power feedback within 1 UI by eliminating the CML summer structure and directly adding a tap branch to the sampler. A digital on-chip foreground training sequence is used to sequentially train TX per-lane deskew, clock swing level, and RX quadrature error corrector (QEC). Six data lanes, two clock lanes, and one replica lane for testing are implemented using an on-chip 2-mm channel in a 28-nm CMOS technology. In the presence of 200-mVpp 120-MHz sinusoidal supply noise injected at TX, horizontal and vertical eyes with CR-PAM3 are measured as 0.34 UI and 121 mV at BER $\lt 10^{-12}$ , while the conventional PAM3 eye is closed.