A μ-NMC-Δ-IMC Heterogeneous STT-MRAM Compute-in-Memory Macro Using Δ-Clamping Bit Reduction for Noise-Tolerant Bayesian Neural Networks

Nonvolatile compute-in-memory (nvCIM) macros integrate memory and computation to enable high-density multiply-and-accumulate (MAC) acceleration for inference tasks on low-power edge artificial intelligence (AI) devices. Bayesian neural networks (BNNs)—which represent weights with mean ( $\mu $ ) and variance-derived deviation ( $\Delta $ )—have emerged as a promising inference model to enhance robustness against noisy real-world inputs. However, deploying BNNs on nvCIM platforms poses several design challenges: 1) ensuring reliable in situ $\Delta $ -weight generation using stochastic memory devices under write-monitor sense margin (WM-SM) degradation; 2) balancing inference accuracy against energy efficiency in dual-weight MAC operations; 3) preventing in-memory-compute (IMC) MAC sense margin (SM) degradation in large memory arrays; and 4) avoiding excessive MAC energy consumption due to bit-level $\Delta $ -weight redundancy. This work addresses these challenges using a heterogeneous nvCIM macro featuring four key schemes: 1) self-compare write-termination (SCWT); 2) a heterogeneous nvCIM structure using near-memory compute (NMC) for $\mu $ -compute and IMC for $\Delta $ -compute ( $\mu {N}$ - $\Delta {I}$ ); 3) 2-D clamping-voltage scaling with sense margin compensation (2D-CVS-SMC); and 4) $\Delta $ -clamping bit reduction (DCBR). A 4.125-Mb macro fabricated using foundry-provided 22-nm spin-transfer-torque magnetic random access memory (STT-MRAM) supports 8-bit MAC operations with 18-ns MAC computing latency, 120.8-TOPS/W energy efficiency, and noise-tolerant BNN inference—demonstrating its effectiveness for next-generation edge AI applications.