Bit Encoding Topologies for High-Frequency QR-ZVS Talkative Converters

Power and Signal Dual Modulation (PSDM) enables low-cost Power Line Communication (PLC) by embedding data into the switching behavior of power converters. However, most existing implementations operate at low switching frequencies (i.e., kHz), limiting bit rates to the kbit/s level and restricting applicability in high-speed communication scenarios. Achieving bit rates beyond 1 Mbit/s requires MHz-range switching frequencies. While wide bandgap devices such as GaN can support such high switching frequencies, conventional hardswitched operation leads to considerable switching losses and elevated Electromagnetic Interference (EMI). This work investigates high-speed data encoding strategies for Quasi-Resonant Converters (QRCs) under Zero-Voltage Switching (ZVS), targeting efficient and EMI-reduced PSDM. In particular, the challenge of preserving ZVS across both mark and space frequencies in Frequency Shift Keying (FSK)-PWM modulation is addressed. Two complementary approaches are proposed: selecting frequency pairs that inherently fulfill ZVS and introducing multiple resonance cycles to adaptively maintain ZVS at different switching frequencies. The encoding methods are experimentally validated on both buck and boost QR-ZVS converters. Results confirm that soft-switching not only supports reliable high-speed bit encoding but also ensures efficient, EMI-optimized power conversion, highlighting the feasibility of MHz-range PSDM for real-time communication and control.