Efficient Topology Reconfiguration Algorithm for Multiprocessor Arrays Driven by Clustered Faults

As integration density increases, topology reconfiguration has emerged as a critical fault-tolerant technique for on-chip multiprocessors. To the best of our knowledge, existing methods for handling processor element (PE) faults in NoC-based multiprocessor arrays primarily target random faults, lacking effective strategies to handle clustered faults. To address this problem, this paper proposes a fast two-stage algorithm for constructing a high-performance, load-balanced logical topology. First, a diagonal-based fault replacement mechanism is introduced to minimize compensation paths for clustered faulty PEs. Second, an innovative candidate region selection strategy is proposed to replace faulty PEs, generating an initial topology with fewer row and column shifting operations. Finally, a novel Hawk-Tabu search algorithm is developed to further enhance communication performance through global search and local refinement of the logical topology. Experimental results show that, compared to state-of-the-art algorithms, the proposed approach reduces communication latency by an average of 10.01%, congestion by 10.37%, and fault-shifting hop count by 13.31% under a 64 × 64 topology with 7 × 7 clustered faults, while also achieving over 90% reduction in reconfiguration time. The proposed algorithms not only improve communication performance by alleviating latency and congestion issues but also enhance the efficiency of reconfiguration.