HARD: A Heterogeneous Last Level Cache Architecture with Readless Hierarchical Tag and Dynamic-LRU Policy

This paper proposes a Heterogeneous Last Level Cache Architecture with Readless Hierarchical Tag and Dynamic-LRU Policy (HARD), designed to enhance system performance and reliability by leveraging the complementary advantages of Static Random-Access Memory (SRAM) and Spin-Orbit Torque Magnetic Random-Access Memory (SOT-MRAM). In the Data RAM, by integrating SOT-MRAM, HARD increases cache capacity under the same area constraints, effectively alleviating performance bottlenecks caused by memory access latency. To better manage the designed Data RAM, we introduce a Dynamic Least Recently Used (Dynamic-LRU) policy, which dynamically adjusts data placement based on access patterns, storing access-intensive data in the SRAM region while migrating access-sparse data to the SOT-MRAM region. This approach not only ensures the performance of the last level cache in high-speed access scenarios but also optimizes storage resource utilization and significantly reduces write pressure on SOT-MRAM. Furthermore, in the Tag RAM, to address the read disturbance issue of SOT-MRAM, we introduce a readless hierarchical tag structure. This structure also employs a heterogeneous design of SRAM and SOT-MRAM, reducing unnecessary matching operations through hierarchical architecture and readless comparison schemes, thereby lowering energy consumption and improving the reliability of the Tag RAM. Experimental results demonstrate that HARD excels in complex data access scenarios, achieving a 40.6× improvement in Mean Time To Failure (MTTF) for the Tag RAM and a 6.3% reduction in miss rate attributed to the increased cache capacity under the same area budget for the Data RAM, offering an efficient and scalable cache solution for high-performance computer architectures.