64-Bit Multiplier Accumulator Unit using Enhanced Vedic Multiplier

Very Large-Scale Integration (VLSI) is the process of embedding complex functionalities into a compact silicon chip by integrating a vast number of transistors. As electronic devices demand faster processing and lower energy consumption, VLSI designers focus on optimizing circuits for key parameters such as power consumption, chip area, and processing delay. Among the critical hardware blocks in modern computing and embedded systems is the Multiply-Accumulate (MAC) unit, which plays a vital role in tasks such as image processing, machine learning, and digital filtering. Efficient MAC design is crucial for improving overall system performance in power-sensitive applications. This work presents a Verilog-based 64-bit MAC unit design that emphasizes power and speed optimization. The proposed architecture achieves a $\mathbf{1 5 . 7 2} \boldsymbol{\%}$ improvement in delay, with a $6.07 \%$ increase in chip area and $3.45 \%$ increase in power consumption when compared to a conventional baseline implementation.