Low Latency based Floating Point Multiplier using Parallel Prefix Adders

Floating point multiplication is a fundamental operation in various computational systems, including digital signal processing, computer graphics and image processing. Floating point multipliers specifically deals with multiplying floating point numbers, which are numbers represented in a format that can handle a wide range of values which follows the IEEE-754 standard. The multiplier face challenges in speed and power consumption due to complexity in the addition stage. Usually, a carry save adder is used in the addition stage, which has large delay in its final stage. To address this, the parallel prefix adders are examined to optimize the addition step. These adders are used in exponent addition as well as in the mantissa addition stage. Parallel prefix adders (PPA) have optimal delay performance at a cost of area overhead. A modified parallel prefix adder is proposed and is integrated into floating point multiplier architecture. This design achieves lower delay, power usage and area in comparison to the existing adders. Therefore, this provides improved performance. The proposed designed has obtained 22.34% less delay compared to the carry save adder. Verilog HDL is used to design the structure and is synthesized using Xilinx Vivado tool to analyze its power, area and delay.