High Speed 2d FIR Filter with Improved Vedic Multiplier Approaches

Multipliers play a significant role in real-time mathematical and logical submission, as well as arithmetically based logical circuit design. Digital logic gate systems require Vedic multipliers as fundamental building blocks of logic gates. In the previous logic circuit design, there were several limitations, such as low power consumption, complex processing circuit design, and slow processing speed. To solve these limitations, a 2D FIR filter was used to enhance the digital signal processing performance. Memories contain both undesirable data, such as signal noise, and desirable data with a certain reliability. A digital filter alters or enhances specific features by applying technical operations to a discrete-time signal sample. Regardless of the number of taps, a multiplier core unit is used to create an adaptive FIR filter with a timesharing multiplier architecture, and filter design controls the phase-shift and loss during insertion and rejection. The output gains in power, area, Area Delay Product (ADP), and Power Delay Product (PDP) as compared to current designs. Compared to the most efficient available methods, it uses 64.45% less power, occupies 61.4% less space, consumes 35.35% less ADP, and utilizes 35.64% less PDP.