Static Timing Analysis on Retinex RTL Design

Enhancing images captured in low-light conditions is critical for applications such as surveillance, medical diagnostics, and autonomous systems, where clear visual information is essential. Conventional enhancement techniques, including Retinex-based approaches, often deliver good results but are computationally demanding, making them unsuitable for real-time use on embedded platforms. This work presents a hardware-efficient Retinex-based enhancement system designed for real-time image processing on a Xilinx Virtex-5 FPGA. The proposed design processes $264 \times 264$ images from the LOL dataset, employing maximum channel extraction, multi-stage illumination estimation with an edge-preserving filter, and reflectance reconstruction followed by tone adjustment. To further improve image stability and suppress artifacts, batch normalization and ReLU activation are integrated into the pipeline. The architecture, developed in Verilog HDL and verified using ModelSim, achieves 60 frames per second while utilizing only 5998 LUTs, 4661 registers, and 15 DSP slices. Timing analysis confirms that all design constraints are met, with a worst negative slack of 0.039 ns and worst hold slack of 0.056 ns. These results demonstrate a lightweight and lowlatency solution well-suited for real-time image enhancement on embedded vision systems with limited computational resources.