Design Methodology of Sizing Power MOSFETs and Optimising Phase Counts in Multiphase DC-DC Converter for Maximising Power Efficiency

This paper presents a design methodology of sizing power MOSFET switches with optimised phase counts to enhance the efficiency profile over a wide load range in multiphase DC-DC converters. In the conventional approach, identical sizes of all phases exhibit a large variation in power efficiency, especially over a wide load range. In the proposed method, power efficiency is improved in the entire load range by adopting appropriate sizing of the power MOSFETs in each phase. It also precisely determines the number of active phases and partitions the entire load range into sub-ranges. To further reduce the design effort, a discriminant-assisted process is introduced to quickly verify the feasibility of input specifications by evaluating the sign (positive or negative) of the discriminant. This confines the search space for the minimum effective equivalent resistance of the active phases while significantly reducing the design iteration time as required in the conventional trial-and-error approach. Various design scenarios are considered to determine the power MOSFET sizing using the proposed methodology. Among them, a variable baseline in different load sub-ranges maximises the power efficiency with an appropriate number of phase counts. To experimentally validate the proposed methodology, a 3-phase current-mode DC-DC converter is implemented in a standard 180 nm CMOS technology with optimised power MOSFET switches. The converter operates at a switching frequency of 20 MHz, an input voltage $V_{IN}$ of 2.7–3.3 V, and an output voltage $V_{O}$ of 1.2 V. The measured result shows a flat efficiency profile with $\sim$ 1% variation in the full load current range of 200mA to 1.4A.