iEEG Seizure Detection with a Sparse Hyperdimensional Computing Accelerator

Implantable devices for reliable intracranial electroencephalography (iEEG) require efficient, accurate, and realtime detection of seizures. Dense hyperdimensional computing (HDC) proves to be efficient over neural networks; however, it still consumes considerable switching power for an ultra-low energy application. Sparse HDC, on the other hand, has the potential of further reducing the energy consumption, yet at the expense of having to support more complex operations and introducing an extra hyperparameter, the maximum hypervector density. To improve the energy and area efficiency of the sparse HDC operations, this work introduces the compressed item memory (CompIM) and simplifies the spatial bundling. We also analyze how a proper hyperparameter choice improves the detection delay compared to dense HDC. Ultimately, our optimizations achieve a $1.73 \times$ more energy- and $2.20 \times$ more area-efficient hardware design than the naive sparse implementation. We are also $7.50 \times$ more energy- and $3.24 \times$ more area-efficient than the dense HDC implementation. This work highlights the hardware advantages of sparse HDC, demonstrating its potential to enable smaller brain implants with a substantially extended battery life compared to the current state-of-the-art.