Efficiency Comparison of FVF-Based LDO Voltage Regulators for Ultra-Fast Response Time

This paper compares, as a function of the efficiency, the small-signal performances of two output stage topologies for the development of ultra-fast response time Low-Dropout regulators (LDOs), based on the Flipped-Voltage Follower (FVF) cell. Although one of the alternatives achieves an higher efficiency for a given bandwidth, it suffers from reduced phase margin. To solve this issue, a technique able to extend the output stage bandwidth with improved efficiency and phase margin is presented. The implementation of a schematic-level prototype LDO in a $28-\mathrm{nm}$ bulk CMOS technology, which exceeds state-of-the-art dynamic performances, confirms the effectiveness of the proposed solution.