Design and Simulation of a 64 Gb/s PAM-4 Wireline Receiver in 22 nm CMOS

We report on the design of a receiver for high-speed I/O in 22nm CMOS compliant with the PCIe 6.0 standard at $64 \mathrm{~Gb} / \mathrm{s}$ with PAM-4 coding. A quarter-rate architecture is considered, implementing equalization strategies such as Continuous-Time Linear Equalization (CTLE) and Decision-Feedback Equalization (DFE, direct). The latter is fully adaptive thanks to the use of error samples. The Clock-and Data-Recovery (CDR) circuit controls an array of phase interpolators working at 8 GHz. For most of the building blocks, we report post-layout simulation results. Simulations including selected circuit blocks, behavioral models and the RTL are used to assess the performance of the whole receiver including the CDR and the fully-adaptive algorithms.