A 6–33-GHz Half-Nanosecond True-Time Delay Line With Gain Compensation for Wideband Large-Scale Antenna Array

This article presents a path-selecting true-time delay (TTD) circuit for wideband large-scale antenna arrays. An in-depth system-level analysis of wideband arrays is conducted to demonstrate the advantage of hybrid array system steered by both phase shifters and TTDs. The corresponding TTD design requirements are derived to enable proper operation of such arrays. The proposed T-coil peaking amplifiers are incorporated to compensate for the steep frequency-scaling losses introduced by the large number of delay lines, thereby ensuring a flat gain across an ultra-wide bandwidth. A detailed design methodology for the T-coil network is presented, and multi-coil coupled floorplan are utilized to facilitate compact layout implementation. In the high-delay path, field-reinforced floorplan are adopted for artificial transmission lines to enhance area efficiency, while in the low-delay path, distributed loss-shaping networks are introduced to mitigate loss variations across different delay states. The proposed TTD circuit is fabricated in 65-nm bulk CMOS, occupying a compact chip area of 1.6 $\mathrm {\times }$ 1.2 mm². It achieves a measured delay range of half a nanosecond with 6-bit resolution across 6–33 GHz. The losses from delay lines are effectively compensated, yielding in an overall gain of 0 dB. The combination of wide bandwidth, large delay range, and low loss makes the proposed TTD circuit well-suited for wideband applications.