Comparative Analysis of Point and Line Tunneling TFETs with Ge/Si Heterostructure

Tunnel field-effect transistors (TFETs) are a promising alternative to conventional MOSFETs for low-power applications due to their ability to achieve a sub-60 mV/dec subthreshold swing. However, a detailed comparative analysis of different tunneling mechanisms, specifically line and point tunneling, remains a critical gap in the literature. This study addresses this by presenting a comprehensive comparison of Ge/Si heterojunction TFETs, with separate structures optimized for each tunneling mechanism (Ge source, Si channel/drain). Our simulations reveal that the line tunneling device (D2) exhibits superior performance compared to the point tunneling device (D1), demonstrating a higher on-current (3×10⁻⁵ A), lower off-current (5×10⁻¹⁸ A), a higher current ratio (6×10¹²), a lower subthreshold slope (18 mV/dec), and a lower threshold voltage (0.22 V). These performance enhancements are attributed to a larger tunneling space and a stronger electric field in the line tunneling configuration. Furthermore, the D2 device shows reduced ambipolar conduction and improved temperature stability. These findings highlight the significant advantages of line tunneling and provide a clear pathway for designing high-performance TFETs.