A Novel Approach to Low Power Multiplier and Comparator Design using GDI Logic

Power efficiency has emerged as a key concern with the increasing demand for high-speed mobile computing devices, particularly in essential components like multipliers and comparators. Battery life and overall performance are greatly impacted by these elements. In contrast to conventional CMOS designs, this project offers a low-power comparator design that uses GDI (Gate Diffusion Input) logic, which lowers power consumption, area, and delay. The proposed comparator, implemented using 18 nm FinFET technology, shows improved performance and delay Using 18 nm FinFET technology, the suggested GDI-based comparator and multiplier reduced power by 85% and latency by 42% when compared to CMOS devices. Low-power embedded applications can benefit from the tiny design's 69% area reduction.