SoC Integration and Verification of a Gigabit Ethernet Controller with RGMII

Modern electronic equipment for miniaturization, low power consumption, high performance requirements are increasingly high, the need to achieve a variety of functions in a limited space, and SoC (System on Chip, System on Chip to) just to meet this demand, and highly integrated SoC in the cost of a single chip is lower than the multi-chip program, so the SoC integrated design is rapidly becoming the mainstream of the industry. In the field of IoT chips, Gigabit Ethernet has become the preferred interface technology for intelligent terminals to realize networking with its 1Gbps high transmission rate and high bandwidth, of which GMAC (Gigabit Media Access Controller) is the core component of Gigabit Ethernet. Traditional MACs use GMII and MII to connect Ethernet physical layer chips, but the number of pins on these interfaces is too high, which is not favorable to the integration and design of modern SoCs. In order to solve the problem of increased PCB manufacturing cost and high wiring density caused by the excessive number of pins, this paper utilizes the RGMII as a protocol converter on a conventional Ethernet controller and integrates the RGMII-based Gigabit Ethernet controller into an SoC, which maintains the throughput of 1G bps through dual-edge clock multiplexing and is compatible with $\mathbf{1 0 M} / \mathbf{1 0 0 M b p s}$ at the same time, which reduces the number of pins by about 50 percent compared to the existing GMAC using the GMII interface. and finally, uses the VIP provided by Synopsys (Verification Intellectual Property (VIP) to build a GMAC verification platform, according to the function and structure of the design to be tested to design the other components of the platform, verification of the basic transmit and receive paths and through the MDIO (Managemrent Data Input/Output) interface to configure Ethernet Physical (PHY) chip internal registers, read PHY link status correctly.