Influence of Gate Oxide and Silicon Sheet Thicknesses on Forksheet Electrical Parameters from 25 to 150°C

This work investigates the impact of gate oxide (Xox) and silicon sheet (HFS) thicknesses on the electrical parameters of forksheet transistors through numerical simulation. A simulation model was developed and validated against experimental data at three different temperatures $(25^{\circ} \mathrm{C}, 100^{\circ} \mathrm{C}$ and 150° C), demonstrating strong agreement in terms of drain current as a function of gate voltage and the extracted parameters. The study shows that increasing HFS improves both maximum $(\mathbf{g m}_{{\max}})$ and saturation $(\mathbf{g m}_{\text{sat }})$ transconductance due to enhanced lateral current paths. Conversely, reducing Xox strengthens gate-channel coupling, resulting in better electrostatic control, higher transconductance, and improved transistors efficiency (gm/Id). Threshold voltage (VT) decreases with increases in either HFS or Xox, and DIBL is mitigated by reducing these dimensions, with both trends consistent across all tested temperatures $\left(25^{\circ} \mathrm{C}-150^{\circ} \mathrm{C}\right)$ and bias conditions. These results highlight the critical role of vertical design parameters in forksheet optimization.