Gate Resistance Optimization for High-Frequency Operation of Emerging SiC MOSFET Technology

A SiC MOSFET is a suitable replacement for a Si MOSFET due to its lower on-state resistance, higher switching speed, and higher breakdown voltage. However, certain precautions are necessary when operating at high switching frequencies due to parasitic elements, which contribute to increased switching losses, electromagnetic interference (EMI) generation, and turn-off overvoltages. In this context, this work proposes an approach to balance and minimize these effects by modifying the gate resistance in the SiC MOSFET gate driver circuit. For this purpose, SPICE simulations were carried out using PSIM and LTspice software, with advanced models provided by Wolfspeed. The analyzed SiC MOSFET was the C3M0021120K model, featuring 1.2 kV technology. Switching losses were evaluated using a double pulse test circuit, while EMI and overvoltage effects were analyzed in a half-bridge circuit operating at 200 kHz. The results show that a proper choice of gate resistance can reduce switching losses. However, it can also intensify overvoltage and EMI effects during transistor turn-off, which may damage the device or interfere with the operation of adjacent circuits.