Improved ESDFET Compact Model Incorporating Transient, Temperature, and Body Bias Effects

In this work, we present an improved compact model for electrostatic discharge field-effect transistors (ESDFETs) that accurately captures key snapback characteristics including triggering voltage ( ${V}_{{t}{1}}$ ), current ( ${I}_{{t}{1}}$ ), hold voltage ( ${V}_{{h}{1}}$ ), and hold current ( ${I}_{{h}{1}}$ ). The model incorporates the effects of gate and body bias, temperature, and input rise time on these critical parameters. The model is simple, provides explicit parameters for ${V}_{{t}{1}}$ and ${I}_{{t}{1}}$ control, and can be readily implemented with any standard process design kit (PDK) model. The transition to the negative differential region during snapback is smooth and continuous. The model is extensively tested with numerical simulations as well as experimental data, showing excellent ability to capture device behavior over a wide range of operating conditions.