Fast FPGA-Based Implementation of the QP-Dyn Stream Cipher using High-Level Synthesis

The relevance of secure communication continues to grow alongside the increasing volume of data requiring protection. In this context, high-speed encryption plays a crucial role. This work presents the FPGA implementation of the QP-DYN stream cipher, which leverages Anosov dynamical systems to implement a Random Number Generator used for encryption and decryption. Using the Vitis High-Level Synthesis (HLS) flow, we design a pipelined ciphering kernel that serves as the core building block of a data-parallel architecture. By instantiating multiple replicas of this kernel, the throughput can be scaled to meet performance requirements. Experimental results from real hardware execution demonstrate that the proposed design achieves high throughput, reaching up to 34 GB/s with eight parallel QP-DYN instances.