GCN-Driven CUDA Parameter Optimization for Parallel Triangle Counting in Graphs

Determining optimal CUDA block size configurations represents a critical challenge in GPU-based graph processing. The block size directly impacts execution efficiency by balancing kernel launch overhead and GPU occupancy—with our experiments showing performance variations of up to 24x. Existing approaches rely on architectural constraints such as static API-based prediction methods that fail to account for the dynamic memory requirements of graph algorithms, which vary significantly based on graph topology. We propose a novel Graph Convolutional Network (GCN) approach that predicts optimal block sizes (64, 128, 256, 512, or 1024 threads) for CUDA graph algorithms using only the graph edge list as input. Our three-layer GCN model uses node degree as the primary feature, capturing the relationship between graph structure and execution performance. Trained on over 100 diverse networks from multiple domains (social, biological, web, road networks, etc.), our model effectively learns how topological characteristics influence memory access patterns and workload distribution. Our model predicts optimal CUDA block size with an accuracy of 63%. When the model fails to predict the optimal block size, it typically selects a suboptimal size that is adjacent to the optimal configuration. Experimental results demonstrate that our GCN-based model significantly outperforms fixed block size strategies, achieving up to 5.3× mean performance improvement across diverse graph types. This work bridges graph learning and high-performance computing, enabling automatic parameter tuning without exhaustive empirical search, and opens avenues for further optimization in graph algorithm acceleration.