Benchmarking of FERAM based memory system by optimizing ferroelectric device model

We present a framework for design technology co-optimization (DTCO) of the main memory system with 1T1C FERAM as an alternative to DRAM. We start with the ferroelectric capacitor device model and perform array level memory circuit simulation. Then we map the circuit level metrics to system level simulators to analyze the performance enhancement of using FERAM as main memory. We demonstrate the performance boost and power savings that can be achieved at the system level by improving individual device characteristics and modifying circuit architecture. We have estimated that on average more than 14% improvement in instruction per cycle and 21% reduction in energy consumption can be achieved by substituting DRAM with FERAM equipped with a ferroelectric capacitor having optimal polarization switching voltage of 1:5V.