An SAR-Assisted Noise-Shaping Pipeline ADC With Gain-Boosted Cascoded Floating Inverter Amplifier

This brief presents a successive approximation register (SAR)-assisted noise-shaping (NS) pipelined analog-to-digital converter (ADC) with the reusing feedback capacitor (RFC) technique. With the proposed RFC technique, the feedback capacitor can simultaneously accomplish the 1st-stage residue transfer, the 2nd-stage quantization error extraction and feedback, and reference voltage matching, which reduces circuit complexity and enhances linearity. To mitigate the noise leakage resulting from gain error, a single-stage closed-loop gain-boosted cascoded floating inverter amplifier (GBCFIA) with 85-dB open-loop gain is proposed. The GBCFIA demonstrates a combination of robustness, high accuracy, and enhanced energy efficiency. Fabricated in a 65-nm CMOS process, the ADC prototype achieves a measured 78.5-dB signal-to-noise and distortion ratio (SNDR) in a 250 MS/s at an oversampling ratio (OSR) of 8. With 2.96-mW power consumption, it achieves an SNDR-based Schreier figure of merit (FoM) of 175.7 dB.