Stability-Enhanced Low-Dropout Regulator with High PSRR in 40-nm CMOS for System-on-Chip Applications

Power supply noise can significantly degrade the performance of complex systems by reducing the signal-to-noise ratio (SNR). To address this, a low-dropout regulator (LDO) with both high power supply rejection ratio (PSRR) and robust stability under large load currents is essential. Conventional LDOs often face a trade-off between achieving high PSRR and maintaining stability, especially at large load currents and wide bandwidths. This work presents a simple yet effective LDO design approach that achieves excellent PSRR without compromising stability, even under large load current conditions. Two novel compensation techniques, adaptive zero compensation (AZC) and DC-coupled zero compensation (DCC-ZC), are introduced to enhance stability margins. Stability is rigorously evaluated under process and temperature variations, as well as varying equivalent series resistance (R_ESR), load equivalent series inductance (L_ESL), and output capacitance. The proposed design demonstrates a phase margin exceeding 45 degrees and a gain margin greater than 10 dB in worst-case scenarios. Fabricated in 40-nm bulk CMOS technology, the LDO achieves PSRR greater than 60 dB up to 5 MHz and supports load currents up to 250 mA. It also delivers excellent line and load regulation, making it well suited for noise-sensitive system-on-chip (SoC) applications that demand both high dynamic performance and enhanced stability.