Prompting for Power: Benchmarking Large Language Models for Low-Power RTL Design Generation

As system complexity and energy constraints tighten in modern SoC designs, there is a growing need for early-stage RTL generation tools that incorporate power optimization techniques. This paper presents a comprehensive evaluation of large language models (LLMs) on their ability to generate power-aware Verilog RTL. We systematically assess multiple LLMs for their effectiveness in synthesizing RTL that reflects key low-power design strategies such as clock gating, operand isolation, and logic restructuring. To facilitate this evaluation, we introduce a curated dataset containing: (1) baseline RTL modules, (2) corresponding low-power optimized versions, (3) associated power-aware prompt templates, and (4) LLM-generated RTL completions. We analyze the generated RTL using industry-standard EDA tools to measure functional correctness, power consumption, and the presence of power-aware constructs. Our results highlight notable differences in model performance, reveal the impact of prompt design on power optimization effectiveness, and demonstrate that prompt-guided LLMs can partially replicate human-like power-aware design intent. This work provides the first systematic study of LLMs for low-power RTL generation and offers a dataset and methodology to benchmark future research in this direction.