Design and Analysis of a 1-Bit Comparator for Low Power VLSI Systems

In contemporary VLSI systems, the requirement for high-speed, low-power digital circuits has made the design of effective arithmetic and logic units crucial. Processors and communication systems depend on comparators, which need to be optimized for space, speed, and power. Using a hybrid technique that combines Transmission Gate Logic (TGL), Gate Diffusion Input (GDI), and Pass Transistor Logic (PTL), this paper suggests a one-bit comparator. To reduce parasitic capacitance and transistor count, the design uses a 6T-MUXbased full adder. It also uses a TGL-based AND gate to increase output speed and a GDI structure to improve logic efficiency while using less power. The circuit is simulated with Spectre and constructed in Cadence Virtuoso with the GPDK 90 nm technology node. Without sacrificing size or performance, the results provide a 58.7 % power reduction and a 31.2 % delay improvement over traditional CMOS comparators. The design is now appropriate for low-power applications of the future. Future development will involve adopting advanced technology nodes and expanding to multi-bit comparators.