A 6.8-to-14.4-GHz Fractional-N CPPLL Featuring a Slide-Dithering-Based DTC Nonlinearity Calibration With Self-Clamping DTC Achieving −65.8-dBc Fractional Spur at 1.6-kHz Offset

This article presents an octave-tuning fractional- $N$ charge pump phase-locked loop (PLL) achieving low fractional spur and low jitter in near-integer fractional channels with the help of a background calibration for the nonlinearity of the digital-to-time converter (DTC) based on the proposed slide dithering and a novel DTC structure, termed the self-clamping DTC (SCDTC). The slide dithering modulates the DTC’s nonlinearity to high frequency, allowing it to be precisely extracted after the high-pass PLL transfer function. This technique effectively overcomes the convergence issues encountered in conventional nonlinearity calibration algorithms in near-integer fractional channels. To further expedite convergence, a hybrid least-mean-squares-gear-estimation-and-compensation (LMS-GEC) calibration accelerator is introduced. This accelerator utilizes an LMS estimator to generate an initial value for nonlinearity calibration. In addition, the SCDTC, a new $RC$ -based DTC structure, offers superior noise and linearity compared with conventional counterparts, thereby contributing to the low jitter and low spur performance. Fabricated in 65-nm CMOS, the presented PLL, with a tuning range from 6.8 to 14.4 GHz, measures a fractional spur of −65.8 dBc in the fractional channel with 1.6-kHz offset, owing to the help of the background calibration of the nonlinearity of DTC. Moreover, thanks to the noise advantage of the SCDTC, the spurs-included integrated rms jitter is measured to be 78.0 fs, generating −250.1-dB FoM $\rm _{J}$ and −258.7-dB FoM $\rm _{T}$ in a near-integer channel.