DNL-Based System-Level Modeling of SAR ADC with Built-In Self-Test

This paper proposes a system-level modeling method for a Successive Approximation Register (SAR) Analog-to-Digital Converter (ADC) based on Differential Nonlinearity (DNL)-based built-in self-test (BIST). The aim is to address the issues of traditional testing technology, which relies on external equipment, is costly, and inefficient. A 12-bit SAR ADC systemlevel model is constructed in Simulink, where the proposed method employs capacitor array weight extraction and nonlinear parameters computation to enable real-time detection and dynamic calibration. The BIST module reconstructs the conversion curve to quantify DNL and integral nonlinearity (INL), while a digital compensation algorithm is implemented to eliminate capacitor mismatch errors. Simulation results demonstrate that under ideal conditions, DNL and INL are optimized to ±0.13 LSB and ±0.12 LSB, respectively. When moderate capacitor mismatch, the calibrated DNL range is reduced to -0.58 LSB to 0.79 LSB. Compared to traditional code density analysis, this approach reduces the required test samples from 2.45 million to 4,095 and eliminates the need for external stimulus sources, significantly lowering testing complexity and cost. Dynamic analysis further reveals an effective number of bits (ENOB) of 11.92, validating the model’s precision and reliability. This work provides an efficient and cost-effective solution for highresolution SAR ADC design optimization. Future efforts will focus on enhancing calibration algorithms under complex process variations and refining capacitor mismatch models.